temporal logic verification
[ˈtɛmpərəl ˈlɑːdʒɪk ˌvɛrɪfɪˈkeɪʃən]
nounpl: temporal logic verifications
verificação de lógica temporal
1. A formal method in computer science used to verify that a system's behavior satisfies desired properties over time, using temporal logic languages like LTL (Linear Temporal Logic) or CTL (Computation Tree Logic)
Temporal logic verification ensures that a safety-critical system never enters an unsafe state during its execution.
A verificação de lógica temporal garante que um sistema crítico de segurança nunca entre em um estado inseguro durante sua execução.
2. An automated technique that checks whether a system model satisfies specifications expressed in temporal logic formulas
The engineers used temporal logic verification to validate the railway control system design.
Os engenheiros usaram verificação de lógica temporal para validar o design do sistema de controle ferroviário.
Temporal logic verification is a specialized term primarily used in computer science, software engineering, and formal methods communities in both Brazil and the USA. It is particularly important in safety-critical systems (aerospace, automotive, railway). While technical terminology is largely universal, Brazilian academia often emphasizes model checking tools developed internationally, and the term is becoming increasingly important as Brazilian industries adopt formal verification practices in compliance with international safety standards.
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