temporal logic falsification
[/ˈtɛmpərəl ˈlɑdʒɪk ˌfɔlsɪfɪˈkeɪʃən/]
nounpl: temporal logic falsifications
falsificação de lógica temporal
1. A formal verification technique used to identify and prove that a system does not satisfy specified temporal logic properties by generating a counterexample trace
The engineer used temporal logic falsification to demonstrate that the safety protocol failed under certain conditions.
O engenheiro usou falsificação de lógica temporal para demonstrar que o protocolo de segurança falhou sob certas condições.
2. The process of disproving the correctness of a system model by finding execution paths that violate LTL (Linear Temporal Logic) or CTL (Computation Tree Logic) specifications
Temporal logic falsification revealed a critical bug in the real-time operating system.
A falsificação de lógica temporal revelou um bug crítico no sistema operacional de tempo real.
3. A model checking method that focuses on finding counterexamples rather than proving correctness
Through temporal logic falsification, we identified the deadlock scenario in the concurrent program.
Por meio da falsificação de lógica temporal, identificamos o cenário de deadlock no programa concorrente.
This is a specialized technical term primarily used in computer science, formal methods, and software engineering communities. It is particularly important in safety-critical systems verification (aerospace, automotive, medical devices). The term is language-agnostic in technical contexts and is understood similarly across English and Portuguese-speaking computer science communities. It represents a key concept in automated verification and is commonly taught in graduate-level computer science programs worldwide.
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